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CPU Architectures & Instruction Set Architectures

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What is an Instruction Set Architecture (ISA)?

• Instructions: What operations the CPU can perform (add, load, store, jump)
• Registers: Fast storage locations inside the CPU
• Memory Model: How the CPU accesses RAM
• Addressing Modes: How instructions specify operands
• Data Types: Supported sizes (byte, word, doubleword)

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Major CPU Architectures

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x86-64 (AMD64, Intel 64)

• CISC (Complex Instruction Set Computer)
• Variable-length instructions (1-15 bytes)
• Rich instruction set with complex addressing modes
• Backward compatible with 32-bit and 16-bit code
• Dominant in desktops, laptops, and servers

• General Purpose: RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, R8-R15 (16 registers)
• Instruction Pointer: RIP
• Flags: RFLAGS (status and control)
• Segment: CS, DS, SS, ES, FS, GS

• Ring 0 (Kernel mode) - Full access
• Ring 1, 2 (rarely used)
• Ring 3 (User mode) - Restricted

; Modern x86-64 system call
mov rax, 1          ; syscall number (write)
mov rdi, 1          ; fd (stdout)
mov rsi, msg        ; buffer
mov rdx, len        ; count
syscall             ; invoke kernel

• Mature ecosystem, extensive tooling
• High single-thread performance
• Strong backward compatibility

• Complex, power-hungry
• Large die size
• Proprietary (Intel, AMD)

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ARM (Advanced RISC Machine)

• RISC (Reduced Instruction Set Computer)
• Fixed-length instructions (32-bit in ARMv7, variable in ARMv8 with Thumb)
• Load/Store architecture (only load/store access memory)
• Dominant in mobile, embedded, and increasingly in servers (AWS Graviton, Apple M-series)

• ARMv7 (32-bit): Cortex-A series, used in older smartphones
• ARMv8 (64-bit): AArch64, used in modern phones, Apple Silicon, AWS Graviton
• ARMv9: Latest, with enhanced security (CCA) and AI features

• General Purpose: X0-X30 (31 registers, 64-bit)
• Stack Pointer: SP
• Program Counter: PC
• Zero Register: XZR (always reads as zero)

• EL0 (User mode)
• EL1 (Kernel mode)
• EL2 (Hypervisor)
• EL3 (Secure Monitor)

; ARM64 system call
mov x8, #64         ; syscall number (write)
mov x0, #1          ; fd
ldr x1, =msg        ; buffer
mov x2, #len        ; count
svc #0              ; supervisor call

• Power efficient (critical for mobile)
• Scalable (from microcontrollers to supercomputers)
• Large ecosystem, many vendors

• Fragmentation (many vendors, custom extensions)
• Licensing model (not open)

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RISC-V

• Open-source ISA - Free to use, no licensing fees
• Modular design - Base ISA + optional extensions
• Clean slate - No legacy baggage, designed for modern needs
• Fixed-length 32-bit instructions (with optional compressed 16-bit extension)

“RISC-V is not a CPU, it’s a specification. Anyone can design a RISC-V processor.”

• RV32I: 32-bit integer base
• RV64I: 64-bit integer base
• RV128I: 128-bit (future-proofing)

• M: Integer multiplication and division
• A: Atomic instructions (for synchronization)
• F: Single-precision floating-point
• D: Double-precision floating-point
• C: Compressed instructions (16-bit)
• G: General-purpose (IMAFD combined)

• General Purpose: x0-x31 (32 registers)
  • x0 is hardwired to zero
  • x1 (ra): return address
  • x2 (sp): stack pointer
  • x8 (s0/fp): frame pointer
• Program Counter: PC
• Floating Point: f0-f31 (if F/D extension)

• M-mode (Machine): Highest privilege, firmware
• S-mode (Supervisor): OS kernel
• U-mode (User): Applications

# RISC-V system call
li a7, 64           # syscall number (write)
li a0, 1            # fd
la a1, msg          # buffer
li a2, len          # count
ecall               # environment call

• Open and free: No licensing costs, no vendor lock-in
• Simplicity: Clean, orthogonal design
• Extensibility: Easy to add custom instructions
• Growing ecosystem: Supported by major companies (Google, NVIDIA, Western Digital)

• Immature ecosystem: Fewer tools, libraries compared to x86/ARM
• Limited hardware availability: Mostly embedded/experimental (as of 2024)
• Software compatibility: Existing x86/ARM binaries don’t run

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RISC-V in Operating Systems

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Linux on RISC-V

• Full SMP (Symmetric Multi-Processing) support
• Virtual memory with Sv39/Sv48 page tables
• Device tree support
• KVM hypervisor support

• Debian, Fedora, Ubuntu, Arch Linux all have RISC-V ports
• Embedded: Yocto, Buildroot

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Why RISC-V Matters for OS Development

1. Educational: Clean ISA makes it easier to learn OS internals
2. Customization: Add domain-specific instructions (crypto, AI)
3. Sovereignty: Countries/companies can design their own CPUs
4. Innovation: Lower barrier to entry for new CPU designs

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RISC-V vs x86 vs ARM: OS Perspective

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Practical Implications for OS Developers

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1. Context Switching

• x86-64: ~20 registers + FPU state
• ARM: 31 GP registers + NEON/SVE state
• RISC-V: 32 GP registers + FP state (if present)

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2. System Calls

• x86-64: Arguments in rdi, rsi, rdx, rcx, r8, r9
• ARM: Arguments in x0-x7
• RISC-V: Arguments in a0-a7

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3. Memory Ordering

• x86: Strong memory model (TSO - Total Store Order)
• ARM: Weak memory model (requires explicit barriers)
• RISC-V: Weak memory model (RVWMO - RISC-V Weak Memory Ordering)

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4. Atomic Operations

• x86: lock cmpxchg
• ARM: ldxr/stxr (load-exclusive/store-exclusive)
• RISC-V: lr.w/sc.w (load-reserved/store-conditional)

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The Future: RISC-V Adoption

• Embedded: SiFive, Espressif (ESP32-C3), Bouffalo Lab
• HPC: European Processor Initiative (EPI)
• AI/ML: Custom accelerators with RISC-V control cores
• Automotive: Potential for safety-critical systems

• Software ecosystem needs to mature
• Need more high-performance implementations
• Toolchain and debugging support improving but not yet at x86/ARM level

• China’s push for technological independence
• IoT and edge computing (billions of devices)
• Academic research and education

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Interview Focus

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Resources

• RISC-V Specification
• x86-64 ABI
• ARM Architecture Reference Manual
• Linux RISC-V Port