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Efficient Architectures

Efficient Neural Network Design

The Efficiency Challenge

Think of deploying a neural network like packing for a backpacking trip: you want to bring everything you need, but every gram counts. A model that runs beautifully on an A100 GPU in your data center is useless if it needs to run on a phone, a drone, or a smart camera. Mobile and edge devices have strict constraints:
  • Compute: Limited FLOPs/second — a phone’s neural engine is roughly 100x slower than a server GPU
  • Memory: Small RAM and storage — many edge devices have under 1 GB of available memory
  • Power: Battery limitations — a model that drains 20% battery per hour will never ship
  • Latency: Real-time requirements — users notice anything above 100ms response time
We need models that are:
  • Small (fewer parameters — less storage, faster download)
  • Fast (fewer FLOPs — lower latency, less power draw)
  • Accurate (still useful! — a fast model that is wrong is just fast at being wrong)
The core tension in efficient architecture design: accuracy almost always trades against speed. The art is finding the sweet spot where you lose minimal accuracy for massive speed gains.
Before designing a custom efficient architecture, check if an off-the-shelf model with a width multiplier (e.g., MobileNetV3-Small at 0.75x width) meets your latency budget. Tuning the width multiplier of a proven architecture is almost always a better starting point than building from scratch.

Depthwise Separable Convolutions

The foundation of nearly every efficient architecture. The key insight is a factorization trick: instead of applying one expensive operation, split it into two cheap operations that achieve roughly the same result. Think of it like multiplying 15 x 12 — you could do it directly, or compute (15 x 10) + (15 x 2), which is easier to reason about. Depthwise separable convolutions split a standard convolution into a spatial filtering step (depthwise) and a channel mixing step (pointwise): Standard Conv: O(K2CinCoutHW)\text{Standard Conv: } O(K^2 \cdot C_{in} \cdot C_{out} \cdot H \cdot W) Depthwise Separable: O(K2CinHW)+O(CinCoutHW)\text{Depthwise Separable: } O(K^2 \cdot C_{in} \cdot H \cdot W) + O(C_{in} \cdot C_{out} \cdot H \cdot W)

MobileNet Family

MobileNetV1

MobileNetV2

MobileNetV3


ShuffleNet

ShuffleNet’s key insight comes from a practical observation: group convolutions save FLOPs but create information silos — channels within a group never communicate with channels in other groups. This is like having teams in an office that never talk to each other. Channel shuffle is the “all-hands meeting” that forces cross-group information flow, and it costs essentially zero FLOPs.

Channel Shuffle Operation


EfficientNet

Compound Scaling


GhostNet


Model Comparison

FLOPs alone do not predict latency. Two models with the same FLOPs can differ by 2-3x in actual inference speed due to memory access patterns, parallelism, and hardware utilization. Always profile on your target device. ShuffleNetV2’s design guidelines (G1-G4) were specifically derived from real-device profiling, not FLOP counting, which is why ShuffleNetV2 is often faster than models with lower theoretical FLOPs.

Exercises

Measure actual FLOPs and latency:
Create your own efficient block combining:
  • Depthwise separable convolution
  • Squeeze-and-excitation
  • Residual connection
Benchmark against MobileNetV2 block.
Experiment with different width/depth trade-offs:
  • Wide and shallow
  • Narrow and deep
  • Balanced
Which works best for your task?

What’s Next?

Graph Neural Networks

Learning on graph-structured data

Quantization Deep Dive

Reduce model precision for efficiency